1. Technical Field
The embodiments described here relate to a semiconductor memory apparatus, and more particularly, to a circuit for generating negative voltage in a semiconductor memory apparatus.
2. Related Art
In general, a semiconductor memory apparatus is constituted by transistors. In particular, a transistor included in a memory cell can supply a first negative voltage to a bulk of a transistor to reduce leakage current. Further, the transistor can supply a second negative voltage to a source terminal of the transistor to compensate for an increase in a threshold voltage caused by the first negative voltage supplied to the bulk of the transistor. Here, an absolute value of the first negative voltage level supplied to the bulk of the transistor should always be higher than that of the second negative voltage level in order to prevent the latch-up phenomenon, which damages transistor elements when a voltage level supplied to the bulk of the transistor is higher than a voltage level applied to the source of the transistor.
FIG. 1 is a schematic diagram of a conventional circuit for generating negative voltage of a semiconductor memory apparatus, and FIG. 2 is a timing diagram of a conventional circuit for generating negative voltage. In FIG. 1, the circuit 1 includes a first negative voltage generating unit 40 and a second negative voltage generating unit 80.
The first negative voltage generating unit 40 includes a first detecting unit 10, a first oscillator 20, and a first charge pump 30. The first detecting unit 10 detects a first negative voltage VNN1 level and generates a first detecting signal ‘det1’, and the first oscillator 20 generates a first oscillator signal ‘OSC1’ in response to the first detecting signal ‘det1’. The first charge pump 30 performs a pumping operation in response to the first oscillator signal ‘OSC1’. Here, the first charge pump 30, which performs the pumping operation, generates the first negative voltage VNN1.
The second negative voltage generator 80 includes a second detecting unit 50, a second oscillator 60, and a second charge pump 70. The second detecting unit 50 detects a second negative voltage VNN2 level and generates a second detecting signal ‘det2’, and the second oscillator 60 generates a second oscillator signal ‘OSC2’ in response to the second detecting signal ‘det2’.
The second charge pump 70 performs a pumping operation in response to the second oscillator signal ‘OSC2’, and the second charge pump 70, which performs the pumping operation, generates a second negative voltage VNN2. Here, the first negative voltage VNN1 is voltage supplied to the bulk of the transistor used in all circuits in the semiconductor memory apparatus and the second negative voltage VNN2 is a voltage supplied to the source of the transistor used in specific circuits in the semiconductor memory apparatus. Thus, capacitance of a node supplied with the first negative voltage VNN1 is larger than capacitance of a node applied with the second negative voltage VNN2. Furthermore, the second negative voltage VNN2 reaches a target level earlier than when the first negative voltage VNN1 reaches the target level.
As a result, when the second negative voltage generating unit 80 starts to generate the second negative voltage VNN2 before the first negative voltage VNN1 generated by the first negative voltage generating unit 40 reaches the target level, a reversal phenomenon (a phenomenon where the second negative voltage VNN2 level becomes lower than the first negative voltage VNN1 level) can occur as in “A” in FIG. 2. The latch-up phenomenon, which can damage the transistor, can occur due to the reversal phenomenon. Damage to the transistor can reduce stability and operational reliability of the semiconductor memory apparatus.